(1) Field of the Invention
The present invention relates to a solid state imaging apparatus and a method for fabricating the same, and more particularly relates to a solid state imaging apparatus including a photodiode and a MOS (metal oxide semiconductor) transistor and using a copper interconnect.
(2) Description of Related Art
MOS-type solid state imaging apparatuses represent image sensors in which each of pixels is formed with an amplifier circuit including a MOS transistor and a signal from each of photodiodes is amplified by the amplifier circuit so as to be read out.
Such solid state imaging apparatuses are called as MOS image sensors. Such a MOS image sensor operates at low voltages, consumes less power, and is integrated in one chip together with a peripheral circuit. In view of the above, in recent years, attention has been paid to the MOS image sensors as image input devices, such as compact cameras for personal computers and portable devices.
Such MOS image sensors are currently fabricated under a 0.35-μm-or-more CMOS rule, and one pixel has a size of, for example, 5.6 μm. However, with the growth of needs for reduction in the size and cost of solid state imaging apparatuses and increase in the number of pixels thereof, it will be conceivable that the pixels will become finer and the response speed of pixels will become faster in the future.
To cope with this, there is known a solid state imaging apparatus utilizing a copper interconnect of low resistance suitable for a high-speed operation and reduction in a region of the solid state imaging apparatus in which interconnects are formed.
FIG. 4 is a diagram illustrating an exemplary circuit configuration of a solid state imaging apparatus. This solid state imaging apparatus includes an imaging region 12 in which a plurality of pixels 11 are two-dimensionally arranged on a single semiconductor substrate, a vertical shift register 13 for selecting one row of the arranged pixels, a horizontal shift register 14 for selecting one column of the arranged pixels, and a timing generator circuit 15 for supplying pulses to the vertical shift register 13 and the horizontal shift register 14.
Each of the pixels 11 arranged in the imaging region 12 includes a photoelectric conversion section 31 composed of a photodiode, a transfer transistor 32 for transferring charges produced in the photoelectric conversion section 31, a reset transistor 34 for resetting the charges by ejecting the charges from the pixel 11, an amplifier transistor 35 for detecting the charges transferred by the transfer transistor 32 and outputting a signal, and a select transistor 36 for controlling a timing at which the amplifier transistor 35 outputs the signal. As described above, the pixel 11 is formed with four MOS transistors.
Next, FIG. 5 is a cross-sectional view illustrating a known MOS-type solid state imaging apparatus 50. A region of the MOS-type solid state imaging apparatus 50 corresponding to two pixels (pixels a and b) is shown in FIG. 5. Since the two pixels have the same structure, the pixel a will be principally described.
The MOS-type solid state imaging apparatus 50 is formed using a silicon substrate 51. Each pixel, e.g., the pixel a, is formed with at least one MOS transistor 52 and a photodiode (hereinafter, referred to as PD) 53.
In the MOS-type solid state imaging apparatus 50, the MOS transistor 52 includes source/drain regions (hereinafter, referred to as source/drain regions 54) formed by implanting impurities into the silicon substrate 51 and a gate electrode 56 formed on the silicon substrate 51 with a gate insulating film 55 interposed between the gate electrode 56 and the silicon substrate 51. Although not shown, the MOS transistor 52 is isolated by an isolation region and formed in a region of the silicon substrate 51 in which a P-type or N-type well is formed. Furthermore, impurities are introduced into the silicon substrate 51 to adjust the threshold voltage of the MOS transistor 52. This is also not shown.
Furthermore, a PD 53 is formed by introducing N-type impurities into the silicon substrate 51.
First-level contacts 71 are formed on the source/drain regions 54, respectively, and first-level buried interconnects 72 are formed on the first-level contacts 71 so as to be connected to the first-level contacts 71, respectively. Furthermore, second-level contacts 73 are formed on the first-level buried interconnects 72, and second-level buried interconnects 74 are formed over the second-level contacts 73 so as to be connected to the second-level contacts 73. Moreover, third-level contacts 75 are formed on the second-level buried interconnects 74, and third-level buried interconnects 76 are formed over the third-level contacts 75 so as to be connected to the third-level contacts 75. A layer in which the first-level contacts 71 and the first-level buried interconnects 72 are formed is referred to as a first-level layer, a layer in which the second-level contacts 73 and the second-level buried interconnects 74 are formed is referred to as a second-level layer, and a layer in which the third-level contacts 75 and the third-level buried interconnects 76 are formed is referred to as a third-level layer.
The first- through third-level contacts and buried interconnects are all formed in an interlayer dielectric 60 formed on the silicon substrate 51 in the manner that will be described below. In this relation, the interlayer dielectric 60 has a layered structure of five layers in total.
First, an interlayer dielectric 61 forming the lower part of the first-level layer (hereinafter, referred to as a first-level lower interlayer dielectric 61) and made of silicon oxide is deposited on the silicon substrate 51 and planarized by chemical mechanical polishing. Next, contact holes are formed in predetermined parts of the first-level lower interlayer dielectric 61 and filled with tungsten or the like, thereby forming first-level contacts 71. The first-level contacts 71 are formed to have a height (thickness) of approximately 0.5 μm.
Subsequently, an approximately 0.4-μm-thick interlayer dielectric 62 forming the upper part of the first-level layer (hereinafter, referred to as a first-level upper interlayer dielectric 62) is deposited on the first-level lower interlayer dielectric 61, and interconnect trenches for forming first-level buried interconnects 72 are formed in the first-level upper interlayer dielectric 62 by lithography and etching. Furthermore, the interconnect trenches are filled with a barrier metal of tantalum (Ta) or the like and a conductive film of Cu, and then the barrier metal and the conductive film are planarized by CMP. In this way, approximately 0.4-μm-thick first-level buried interconnects 72 are formed.
Subsequently, a silicon oxide material is deposited on the first-level upper interlayer dielectric 62 to form an approximately 0.6-μm-thick second-level interlayer dielectric 63. The formed second-level interlayer dielectric 63 is planarized by CMP. Next, via contact holes and interconnect trenches are formed in the second-level interlayer dielectric 63 by lithography and etching and then filled with a barrier metal of Ta or the like and a conductive film of Cu. Thereafter, the barrier metal and the conductive film are planarized by CMP. In the above-mentioned manner, approximately 0.3-μm-thick second-level contacts 73 and approximately 0.3-μm-thick second-level buried interconnects 74 are formed.
Subsequently, like the second-level interlayer dielectric 63, the second-level contacts 73, and the second-level buried interconnects 74, a third-level interlayer dielectric 64, third-level contacts 75 and third-level buried interconnects 76 are formed.
Furthermore, a barrier metal of titanium nitride (TiN) and an aluminum (Al) film are formed on the third-level interlayer dielectric 64 and then etched, thereby forming pads (not shown). Thereafter, a passivation film 81 of silicon nitride is formed on the third-level interlayer dielectric 64 and an uppermost interlayer dielectric 65 is stacked on the passivation film 81.
Subsequently, a color filter 82 is formed on the uppermost interlayer dielectric 65, and on-chip lenses 83 are formed on the color filter 82.
Used for such a solid state imaging apparatus 50 are buried interconnects that can be formed to have a smaller thickness than interconnects formed by etching. This reduces the thickness of a layered structure of interconnect layers or any other layers formed on a photoelectric conversion section. This improves the light-reception efficiency of the solid-state imaging apparatus 50.
Furthermore, the use of copper as a material of an interconnect layer restrains the resistance of the interconnect layer from increasing due to the reduced thickness of the interconnect layer.
Japanese Unexamined Patent Publication No. 2003-264281 has been known as one of the known arts of this type.